Stored-program control machine

ABSTRACT

A hierarchical organization of programmable logic arrays permits the control of microprocessor functions to be achieved in a way which allows otherwise wasted clock time to be used. The mostly independent operations of the several PLA&#39;s is organized by &#34;handshake&#34; signals from the latches of one PLA to those of another via AND circuits operative to selectively enable clock signals, in some instances, and data in other instances, to be applied to the latches. The use of the AND circuits enables requisite operations to be achieved with relatively small PLA&#39;s.

FIELD OF THE INVENTION

This invention relates to stored-program control machines and, moreparticularly to semiconductor integrated circuits such asmicroprocessors for implementing such machines.

BACKGROUND OF THE INVENTION

A microprocessor generally is accepted to include various elements of acomputer on a single chip of semiconductor material with the possibleexception of memory (Program and Data Store).

The various processing functions of a microprocessor are carried out inan area of the chip which includes registers and an arithmetic logicunit and is referred to as the data path portion of the chip. Thecooperation between the various elements of the data path portion aswell as the sequences in which those elements cooperate is determined bysequences of outputs generated by a programmable logic array (PLA) andapplied in a manner to control the data path portion of the chip. See"Introduction to VLSI Systems" by Carver Mead and Lynn Conway,Addison-Wesley, 1980 for a full explanation of PLA's.

A PLA includes a decoder section and a read only memory (ROM) sectionwith associated input and output registers respectively. The decodersection is known as an "AND" plane and includes a drive line for eachinput term and one for each complement term. Each of the drive andcomplement lines intersect electrically conducting output lines whichextend into the ROM section where they become "word" lines. The lineswhich intersect the drive and complement lines are called decoder outputlines. At selected intersections in the decoder section, pulldowntransistors are formed. The transistors respond to various input codesto ground selected decoder output lines. The outputs of the AND planethus are determined by the locations and gate connections of pulldowntransistors connected to the decoder output lines.

The ROM section of a PLA also includes output lines which intersect theword lines. Again, pulldown transistors are formed at selected ones ofthose intersections with transistor gates connected to the word lines.In the case of CMOS logic, if the gate of any transistor connected to adecoder output line is at a high (low) voltage, that entire output lineis at a low (high) voltage as is the associated word line in the ROMsection. By a selective placement of transistors in both the decodersection and the ROM section of a PLA, a particular output code appearson the ROM output lines for each input code applied to the inputs of thedecoder section. In this manner, instructions of an input program aredecoded into a sequence of cycle-by-cycle actions. A representation ofthe repertoire of actions is termed a state diagram.

The action to be performed during a give two phase cycle (φ₁ and φ₂) isdefined at the output of a ROM section of a PLA at an output registerclocked during phase φ₂ or a two phase clock cycle. An input register tothe PLA is operative to store, in a φ₁ phase, input data that wereapplied to it during the immediately preceding φ₂ phase.

As the number of operations performed by the elements of the data pathportion of a microprocessor chip increases, so does the requisite numberof cycle-by-cycle actions. The number of distinct actions that a PLA caninvoke is a function of the number of word lies. Consequently, the PLAhas to increase in size in order to invoke an increased number ofactions. Since the available area on a semiconductor chip is limited,the space available for the PLA is also limited. Further, as the PLAincreases in size it operates more slowly and thus limits the clock rateof the entire device. The problem thus is to implement a requisite logicfunction with a PLA of relatively reduced area.

BRIEF DESCRIPTION OF THE INVENTION

The foregoing problem is solved in several ways in accordance with thisinvention. One solution involves the combination of logic circuitry witha PLA to implement the function of a state diagram implemented in theprior art only with a relatively large PLA. In a preferred solution twoor more separate PLA's are copperative in a manner to implement thefunction of a single prior art PLA. Particularly, the interconnection oftwo or more finite state (control program) machines via at least oneelectrical path which may or may not include logic is considered asignificant departure from prior art thinking.

In one embodiment herein the problem is solved by applying the normalclock pulse to the input register of a PLA by way of an AND circuitwhich can be enabled at controlled times in a clock cycle. In theabsence of the AND circuit, whenever a phase φ₁ clock pulse occurs ineach cycle of operation, a PLA output (state) is required to orchestrateoperation of the elements of the data path portion or to orchestrate apause during the next consecutive φ₂ phase operation. Additional ROMword lines are required to generate the same state in a next consecutiveclock cycles, and the repertoire of the relatively large PLA results.The use, for exmaple, of an AND circuit to inhibit the clock permits thenumber of output states to be reduced. Concomitants to this reductionare a reduction in the requisite number of word lines, a reduction inthe requisite PLA area, and an increase in speed.

With the AND circuit present, an enable signal, termed a "wait" signal,can be applied to provide for state continuance during a nextconsecutive φ₁ phase. Pause states and associated word lines areobviated. The inclusion of means for enabling a logic element forapplying a clock pulse to an input register to a PLA is also considereda significant departure from prior art thinking.

The arrangement is particularly useful for a microprocessor whichincludes two or more PLA's each illustratively dedicated to associatedelements in the data path portion of the chip. Each PLA and itsassociated data path elements form a unit of operation (i.e., additionor subtraction) which are operative largely indepedently of one another,being constrained primarily in that other largely independent operationsare necessarily coordinated in order to achieve the usual kinds ofprocessing results. The coordination typically is accomplished by afirst PLA applying an enable "wait" signal to a second PLA. The signaloperates to disable an AND circuit to inhibit an input clock signal tothe second PLA. The coordination of multiple PLA's, particularly witheach PLA having processing elements associated exclusively with it, isconsidered another departure from prior art thinking and leads to apowerful hierarchical PLA control arrangement.

.[.Copending application Ser. No. 233,107 filed on even date herewithfor Marc. L. Harrison discloses the use of logic elements betweenmaster-slave latches for performing processing during otherwise unusedtime which occurs between the φ₁ and φ₂ pulses of a standard clockcycle. The present invention capitalizes on the use of such logicprimarily to reduce PLA complexity by gating timing pulses and/or alsoto achieve such ends by gating data. In both cases, hierarchical PLAcontrols are achieved..].

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows a schematic block diagram of a microprocessor organization;

FIGS. 2 and 3 show a prior art PLA arrangement in some detail and inschematic form, respectively;

FIGS. 5 and 6 show, in some detail and schematically, respectively a PLAarrangement in accordance with one embodiment of this invention;

FIGS. 4 and 7 are state diagrams for the arrangements of FIGS. 2 and 5,respectively; and

FIGS. 8, 9, and 10 are schematic diagrams of alternative embodiments ofthis invention.

DETAILED DESCRIPTION

FIG. 1 shows a semiconductor integrated circuit chip 10 including a PLA,a control, and a data path portion 11, 12, and 13, respectively. FIG. 2shows a prior art arrangement for the PLA portion of FIG. 1. Thearrangement includes the conventional components, namely the decoderportion 14 (the AND plane), the ROM portion 15 (the OR plane), and theassociated input and output buffers 16 and 17, respectively. FIG. 2shows the arrangement in some detail; FIG. 3 shows the arrangementschematically with the addition that the familiar input and outputregisters (latches) 18 and 19 are shown connected to the buffers. FIG. 3also shows two phase clock signals φ₁ and φ₂ being applied to inputregister 18 and to output register 19, respectively.

The circuit typically includes an array of transistors (not shown) inthe decoder and in the ROM sections to define the specific pattern ofbits generated by the output register in response to a particular inputcode as per the representative state diagram. The array of transistorsis not being shown because a discussion of the generation of aparticular pattern of bits is unnecessary to an understanding of theinvention. All that is important here is that the arrangement of FIG. 2shows four word lines 20, 21, 22, and 23 which permit a number ofpotentially different binary output words at the input of outputregister 19.

A simple state diagram for the arrangement of FIGS. 2 and 3 is shown inFIG. 4. The possible input bits S_(o), S₁, and wait are shown in FIG. 3.The possible output bits are N₁, N_(o) and SIG1. Four states are shown,one represented by each of blocks 30, 31, 32, and 33 in FIG. 4. Theoperation represented in FIG. 3 typically requires four word lines inthe decoder and ROM portions of the PLA.

FIGS. 5 and 6 show, in detail and schematically, respectively, a PLAarrangement in accordance with an embodiment of this invention. Acomparison of FIGS. 5 and 2 shows that the arrangement of FIG. 5 hasonly three word lines, namely 120, 121, and 122. The arrangement of FIG.5 does, on the other hand, include an AND circuit 125 connected to aninput 126 to which clock signal φ₁ is applied. An enable signal "wait"is applied selectively to a second input 127 of AND circuit 125. FIG. 7shows the state diagram for the embodiment of FIGS. 5 and 6. It can beseen from a comparison of the state diagram of FIGS. 4 and 7 that thedescribed operations are achieved with fewer word lines and one fewerinput in the arrangement of FIGS. 5 and 6.

AND circuit 125 is shown in FIG. 6 also. The AND and OR planes in FIGS.5 and 6 are designated 211 and 212, the corresponding input and outputregisters being designated 213 and 214, respectively. The wait signal isoperative to gate the clock (φ₁) pulse for the entire input code in thisembodiment.

In a related embodiment of FIG. 8, a plurality of feedback loops areconnected between the output register and the input register 323 and324, respectively, of a ROM section and a decoder section 325 and 326 ofa PLA 327. The feedback loops are designated l₁ . . . l_(n). An ANDcircuit 328 is employed in a manner similar to that shown in FIG. 6. Thepresence of such loops also is implied by the state diagram of FIGS. 4and 7. Consequently, each of the arrangements of FIGS. 3 and 6 mayinclude feedback loops and FIG. 8 is intended to illustrate the presenceof such loops.

FIG. 9 shows an embodiment in which signals in feedback loops betweenthe ROM section of a PLA and the decoder section of the same PLA asshown in FIG. 8 are selectively inhibited by a signal from a second PLA.The figure shows decoder and ROM sections 411 and 412 of a first PLAalong with input and output registers 413 and 414. Decoder and ROMsections 415 and 416 of a second PLA along with input and outputregisters 417 and 418 are also shown. Representative feedback loops 420,421, and 422 interconnect outputs of register 414 to input register 413.Each feedback loop includes an AND circuit, and an output of register418 of PLA #2 is connected to an input of each of the AND circuits. TheAND circuits are designated 130, 131, and 132 for loops 420, 421, and422, respectively.

We have seen that the provision of a control signal to a logic circuitsuch as an AND circuit to selectively enable clock pulses to be appliedto an input register of a PLA results in the realization of a given setof operations with a PLA of reduced size. A like reduction in size isachieved with the embodiment of FIG. 9, again capitalizing on the use ofa logic circuit but in this instance for processing data between φ₁ andφ₂ phases of a clock cycle. For the examples given, a reduction of thenumber of word lines of 25% is achieved. In a practical embodiment, atypical prior art PLA may contain 150 word lines which number is reducedto slightly over 100 by the use of a logic circuit in accordance withthe foregoing discussion. Again size reductions of about 25% areachieved. We will now show that the judicious use of such AND circuitsenables a hierarchical PLA architecture to be achieved, leading toimproved microprocessor operation as well as to a reduction in size.

FIG. 10 shows a portion of a semiconductor microprocessor chip 500 and amemory 501 external to the chip. The microprocessor includes a Main PLA505, a Fetch PLA 506, and an Arithmetic PLA 507. PLA 506 is associatedwith user registers 510, . . . 517 and with associated output tri-statebuffers 510A, . . . 517A. PLA 507 is associated with arithmetic logicunit (ALU) 520. The microprocessor also includes two temporary registers521 and 522, and data bus 525. Data and control inputs and outputs (I/O)units are designated 526 and 527, respectively.

The first illustrative operation of the arrangement of FIG. 10 isdirected at moving the contents of two selected user registers 510 . . .517 to the temporary registers 521 and 522 under the control of FetchPLA 506 and, thereafter, to carry out an "add" operation in ALU 520under the control of Arithmetic PLA 507. Both PLA's 506 and 507 areunder the control of Main PLA 505 during the operation, and the PLA'sare interconnected in a manner to enable clock pulses to be applied toinput registers as described in connection with FIG. 6.

We will adopt the convention that action starts on a (φ₁) clock cycle atwhich time the Main PLA is assumed to receive a valid command input fromcontrol I/O 527. On the next subsequent phase (φ₂), Main PLA 505 appliesits valid output to the input registers 561 and 559 of the Fetch and theArithmetic PLA's 506 and 507. On the following phase φ₁, PLA's 506 and507 have valid command inputs. On the next phase φ₂, the Fetch PLAapplies an output to a selected one of tri-state buffer circuits 510A,511A, 512A, . . . 517A and activates one user register. Outputs from theselected register are applied to bus 525. During this phase, PLA 507enables temporary register 521 to receive data from bus 525.

During the next φ₁ phase (cycle 3), the Fetch and Arithmetic PLA'sreceive a second valid command input. During the following φ₂ phase,data from a second user register is applied to bus 525, and temporaryregister 522 is enabled. The operation to this point has resulted indata in first and second user registers to be stored in first and secondtemporary registers 521 and 522.

The fourth cycle of operation commences on a phase φ₁ during which PLA507 activates temporary registers 521 and 522. Registers 521 and 522apply inputs to ALU 520 during this phase. During the following phaseφ₂, ALU 520 applies a valid output (data) to bus 525, and the Fetch PLAtransfers that data into a selected user register (510 . . . 517). Theoperation to this point results in the addition of two binary numbersstored in two user registers by moving those numbers to temporaryregisters and then driving the numbers through an ALU where additionoccurs. The result is returned to a selected user register over the bus.The operation is summarized in TABLE I:

                  TABLE I                                                         ______________________________________                                        Cycle   Action (Single Cycle)                                                 ______________________________________                                        1    φ.sub.1                                                                          Main PLA receives first valid opcode from I/O                                 527                                                                    φ.sub.2                                                                          Main PLA applies valid output commands to Fetch                               and Arithmetic PLA's                                              2    φ.sub.1                                                                          Fetch And Arithmetic PLA's have valid input                                   command                                                                φ.sub.2                                                                          Fetch PLA enables first selected user                                         register;                                                                     Arithmetic PLA enables first temporary                                        register to receive data from bus;                                            Main PLA outputs 2nd valid commands;                                          assert data valid                                                 3    φ.sub.1                                                                          Fetch And Arithmetic PLA's receive second                                     valid input command                                                    φ.sub.2                                                                          Fetch PLA enables second selected                                             user register                                                                 Arithmetic PLA enables second temporary                                       register to receive data from bus                                             assert data valid                                                 4    φ.sub.1                                                                          temporary registers apply input data to ALU                            φ.sub.2                                                                          ALU applies valid output data to bus,                                         Fetch PLA latches data from bus to user register                  ______________________________________                                    

It is noted that tri-state buffer circuits 510A-517A are enabled byoutputs from PLA 506 applied from output register 562 through a slavelatch designated 562S. Such a latch is employed because register 562 isoperated in a φ₂ phase and circuits 510A-517A are operative in φ₁ and φ₂phases of a subsequent cycle and therefore isolation is required. Asimilar organization is required for PLA 507 in activating slaveregister 550. In each of these cases, a master-slave relationship existsand an opportunity arises for introducing logic in a manner to utilizeunused time. No advantage of such an opportunity is taken in theseinstances. The use of slave latch 557S similarly provides isolation asrequired for latch 550 and permits proper timing operation of temporaryregisters 521 and 522.

ALU 520 performs AND, OR, Add, Subtract, and Complement functions. Ifthe registers 521 and 522 have contents represented by TA and TB,respectively, the functions are symbolized by (TA CR TB), (TA AND TB),(TA+TB), (TA-TB), and (TA), respectively. Five bit register 550determines the function performed and is itself enabled by an outputfrom PLA 507 via line 558. The clock input to register 550 is connectedto the output of AND circuit 552. One input to the AND circuit isconnected to a clock source; the other to an output of output register557 of PLA 507 via line 558. The output from PLA 507 over line 551 isoperative to program register 550 in a manner to enable the various ALUoperations in sequence. The output from PLA 507 over line 558 enables aclock pulse to select the appropriate operation.

Note that the clock to input registers 560, 561, and 559 of PLA's 505,506, and 507 respectively is applied via inputs to AND circuits 563,564, and 565, respectively. The second input to AND circuit 563 isconnected to an output of register 562 of PLA 506. The second input toAND circuit 565 is connected to an output of register 562 also. Thesecond input to AND circuit 564 is connected to an output of data I/O526. The organization of the gated clock pulses is essentially as shownin FIGS. 5 and 6, being operative to selectively disable the ArithmeticPLA from stepping through its state diagram for selecting temporaryregisters and for determining the function of the ALU, etc.

Similarly, AND circuit 564 is operative responsive to a control signalfrom I/O 526 to enable selection of a next subsequent user register ormemory address only when the prior fetch operation is completed. In theabsence of such a signal, the clocks at the input registers 560 and 561of PLA's 505 and 506 are inhibited. The signals may be understood as"assert data valid" signals or "handshake" signals and occur in theabove example at cycle 2, phase φ₂, and cycle 3, phase φ₂. In cycle 2,phase φ₂, the output from register 562 of PLA 506 selects the userregister and enables output register 557 of PLA 507 to select thetemporary register and AND circuit 552 to determine the function of ALU520.

In cycle 3, phase φ₂, the handshake is similar. The input register 560of Main PLA 505 is connected to the output of AND circuit 563 in anarrangement similar to that of AND circuit 564 as noted hereinbefore.The handshake signals from PLA 506 are applied to selectively enable theclock at circuit 563 to permit outputs from PLA 505 to proceed to a nextsubsequent operation as would occur in cycle 3, phase φ₁ in TABLE I.

When the output from the selected user from register (510-512) is anaddress to memory 501, an indeterminate number of cycles of operationmay occur before the address is acquired as in the case, for example,when a disk file is searched. In such a multiple cycle of operation,cycle 2, phase φ₂ of TABLE I is expanded as summarized in TABLE II.

                  TABLE II                                                        ______________________________________                                        Cycle        Action (Multiple Cycle)                                          ______________________________________                                        2      φ.sub.1                                                                             Fetch and Arithmetic PLA's have                                               valid inputs commands                                               φ.sub.2                                                                             Contents of selected user register                                            applied to output latches of                                                  data I/O 526,                                                       φ.sub.1                                                                             No new command - address goes                                                 out on the pins                                                     φ.sub.2                                                                             Address goes from output latches                                              into memory                                                         φ.sub.1                                                                             Memory responds to address,                                                   data ready?                                                         φ.sub.2                                                                             If data not ready, hold Fetch PLA                                             (which in turn holds Main PLA)                                                (i.e., no handshake signal to AND                                             circuit 564;)-Repeat                                                          If data ready, latch input of                                                 data I/O 526 to enable clock                                                  at AND circuit 564.                                                           data from memory applied to                                                   bus 525 for storage in temporary                                              store TA or TB.                                              ______________________________________                                    

In the absence of a gated clock signal at the input registers of theMain, the Arithmetic, and Fetch PLA's, each of those PLA's would have tobe considerably larger as discussed hereinbefore. Moreover, reduction inPLA size (and thus increased speed) is achieved whenever a gated clocksignal is used. The use of a gated clock signal to an input register ofa PLA (as shown in FIG. 6) or the use of a gate to gate data from or toan output register of a PLA (as shown in FIG. 10) achieves like savings.The architectural strategy of the microprocessor determines which gatingmeans is employed or whether both are used in any particular case.

The organization of the PLA's in a control hierarchy permits each PLA toapply successive commands to elements, such as an ALU and temporaryregisters, which are dedicated to it. In this manner, independentindependent PLA's may proceed with successive operations independentlywhere a Main PLA is operative to initiate those independent operations.The handshaking signals indicate that the various independent operationshave been completed, and the next subsequent command is permitted.Concurrent PLA execution resulting in pipelining of data manipulation(parallel processing) thus is achieved. The gating of clock signals tothe PLA's of a microprocessor with a plurality of PLA's organized in ahierarchy is a powerful arrangement leading not only to size and overallspeed advantages, but also to throughput advantages. The last-mentionedadvantage arises because the independent PLA's can utilize cycle timewhich would otherwise be unavailable for use if only a single(relatively large) PLA were to be used.

The implementation of a control hierarchy herein may include a directinterconnection between an output register of one PLA and an inputregister to another. Such an interconnection is represented by line 600in FIG. 10 and may be used in reset operations.

The invention has been described herein to include programmable logicarrays which are state machines having input and output latches. Butthere are other potential elements for use with the invention. Forexample, it is possible to employ the gated clock means and thehierarchical organization in a multiple ROM or ROM/PLA arrangementdirected to the same end. Further, the gating of data or the gating ofclock pulses may be considered embodiments of the use of logic betweenmaster and slave latches. The embodiment of FIG. 9, for example, doesnot show a gated clock. It does show logic circuitry between a masterand a slave latch, which in FIG. 9 are the output register (latch) of afirst PLA and the input register (latch) of a second PLA, respectively.Gated clock means for providing clock signals as shown in FIGS. 6, 8,and 10 also may be considered to constitute logic between a master latchand a slave latch. For example, in the embodiment of FIG. 10, the masterlatch and the slave latch are output and input registers, respectively.In any case, the master-slave relationship exists and logic circuitry isemployed to utilize otherwise unused time. The inclusion of logiccircuitry whether for gating clock signals or for manipulating databetween input and output latches of a plurality of PLA's is consideredparticularly unique herein leading to the powerful PLA control hierarchydisclosed as was mentioned hereinbefore.

What has been described is considered merely illustrative of theprinciples of this invention. Various modifications of the invention canbe devised by those skilled in the art in accordance with thoseprinciples within the spirit and scope of the invention as encompassedby the following claims. Specifically, the invention can be implementedin NMOS, PMOS, pseudoNMOS, CMOS, etc. integrated circuit technology asis apparent to one skilled in the art. Moreover, although the inventionhas been described in terms of enabling a clock pulse or enabling datato be applied to input registers, an alternative mode in whichnormally-present clock pulses are disabled can be implemented to thissame end. Also, other than AND circuits may be used to manipulate dataor the clock in otherwise unutilized time between consecutive clockpulses as described herein. Moreover, the invention need not bepracticed in a single integrated circuit chip. Rather, components may bedefined in more than one chip (or discrete component) and still takeadvantage of unused time as disclosed herein. In addition, as would beapparent to one skilled in the art, more than one input can be employedfor gating a clock signal or data; more than one gate may be used also.

What is claimed is:
 1. An integrated circuit structure including a firstlogic array having an associated input register for supplying firstsignals to said first logic array, and a second logic array having anassociated output register for receiving second signals from said secondlogic array, said input and output registers being operativerespectively in .[.response to.]. first and second .[.phase clockpulses, clock means for applying clock pulses in said first and secondphase.]. .Iadd.clock phases .Iaddend.and means for applying inputs tosaid input register .Iadd.during said first clock phases.Iaddend., saidstructure being characterized by control means.Iadd., .Iaddend.connectedbetween said output register and said input register .Iadd.and.Iaddend.responsive to an output from said output register during.[.each.]..Iadd.a .Iaddend.second phase .[.clock pulse.]..Iadd.,.Iaddend.for controlling modification of selected ones of said.[.second.]. .Iadd.first .Iaddend.signals received in the .[.output.]..Iadd.input .Iaddend.register during the next .[.preceding second.]..Iadd.first .Iaddend.phase .[.clock pulse.]..
 2. An integrated circuitstructure in accordance with claim 1 including a first and a second.Iadd.programmable logic array .Iaddend.PLA .Iadd.wherein said firstlogic array comprises a decoder section of said first PLA and saidsecond logic array comprises a ROM section of said second PLA andincluding clock means for applying clock pulses in the first and secondphases, said structure being further characterized in that said controlmeans is adapted to selectively apply first phase clock pulses to saidinput register responsive to signals from said output register.Iaddend..3. An integrated circuit structure in accordance with claim 2 alsoincluding a third logic array comprising a ROM section and having anassociated output register and feedback loops between outputs of saidassociated output register of said third logic array and inputs to saiddecoder section of said first PLA, said structure being furthercharacterized in that said control means is adapted to selectivelymanipulate signals from said associated output register of said thirdlogic array to said input register of said decoder section of said first.[.logic array.]. .Iadd.PLA .Iaddend.responsive to signals from saidoutput register of said ROM section of said third logic array.
 4. Anintegrated circuit structure including at least first and second PLA'swith first decoder and first ROM sections and with second decoder andsecond ROM sections respectively, said first and second decoder sectionshaving associated therewith first and second input registersrespectively, said input registers including gates and being operativein a first phase of a clock cycle to latch data, said first and secondROM sections having associated therewith first and second outputregisters respectively, said output registers including gates operativein a second phase of a clock cycle to latch data, a clock means forproviding clock pulses in first and second phases, and first controlmeans connected between said second output register and said first inputregister responsive to a first output signal from said second outputregister during a second phase for selectively enabling input to saidfirst input register in the next .[.subsequent.]. first phase.
 5. Anintegrated circuit structure in accordance with claim 4 wherein saidstructure also includes a third PLA having third decoder and third ROMsections with a third input register and a third output registerassociated therewith and operative in first and second phasesrespectively, .[.and third control means connected between said thirdinput register.]., means for applying an output signal from said.Iadd.second .Iaddend.output register .[.of said second PLA.]. to inputs.[.to said.]. .Iadd.of a .Iaddend.third control means during a secondphase for selectively enabling said third input register in .Iadd.the.Iaddend.next .[.subsequent.]. first phase.
 6. An integrated circuitstructure in accordance with claim 5 also including a second controlmeans responsive to an output from said first .[.input.]. .Iadd.output.Iaddend.register during a second phase for selectively enabling saidsecond input register of said second PLA in next subsequent first phase.7. An integrated circuit structure in accordance with claim 6 alsoincluding an input-output latch, a fourth control means responsive to afirst output from said input-output latch during a first phase forselectively enabling said second input register of said second PLA innext subsequent first phase.
 8. A digital processor including first andsecond .Iadd.programmable .Iaddend.logic arrays having first input andoutput and second input and output registers, respectively, a firstfeedback path between at least said first output register and said firstinput register and means for electrically connecting an output of saidsecond output register to an input of said first input register.
 9. Adigital processor in accordance with claim 8 also including at least asecond feedback path between said second output register and said secondassociated input register wherein said arrays and register feedbackpaths implement first and second finite state machines respectively. 10.A digital processor in accordance with claim 8 also including means forelectrically connecting the output of said first output register to theinput of said second input register.